Have you gone through EECS151 and spent many a sleepless night perfecting your CPU, only to watch it get lost in a Github repository? Have you wondered what it'd be like to see your project come to life in real silicon? Or are you simply enthusiastic about design and wanting to learn more about System-on-Chip (SoC)s, end-to-end integration, or the Berkeley open source VLSI ecosystem? If so, keep reading!
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Course Description

This project-based course is a follow up to EECS 151: Introduction to Digital Design and Integrated Circuits, where students will learn principles, components, and methodologies for large scale digital System-on-Chip (SoC) design.

Students who designed a CPU core in the EECS151LA ASIC (application specific integrated circuits) lab will learn how to use Chisel (a hardware description language) and Chipyard (an agile hardware design framework) to integrate their core into a full-scale System-on-Chip (SoC). While covering the basics of end-to-end SoC integration and parametrizable computer architecture, the course is primarily a hands-on experience. A class SoC is planned to be taped out in the open-source Skywater 130nm process at the end of the semester.

Recommended Prerequisites

This rigorous course is designed for students who have completed EECS 151 LA ASIC and/or EE 194/290C (the traditional 'Tapeout' and 'Bringup' courses). Students who instead completed EECS 151 LB FPGA are welcome but may have a higher learning curve and will be working with the cores of ASIC students. Students who have not completed EECS 151 or Tapeout/Bringup are recommended to take this Decal after having completed the course. Those unsure are welcome to email us. We are extremely welcoming to self-motivated students of various backgrounds but do wish to emphasize that background knowledge will be helpful, especially as this is the early iteration of the course.

Course Objectives

As this is an early iteration of the course, the first cohort focuses on a hands-on dive into the Chipyard ecosystem of parameterizable hardware generators, the Chisel hardware description language, and implementation of a Hammer VLSI flow for the open-source SKY130 process development kit. Those with previous tapeout experience may help develop the toplevel flow, while those with EECS151 experience only will work on integrating their ASIC cores into Chipyard with the mentorship of more advanced students. While there may be occasional mini-lectures, the focus of this course is a hands-on project - a real SoC tapeout in the open-source Skywater 130nm CMOS process.

An enrollment form will be made available before the first class. Enrollment will be balanced to ensure an even distribution of experience levels. If there is capacity remaining, students may request enrollment up until the add/drop deadline. Enrollment priority will be given to matriculated students over concurrent enrollment students due to department policy. Please contact us for details and concerns.