Have you gone through EECS151 and spent many a sleepless night perfecting your CPU, only to watch it get lost in a Github repository? Have you wondered what it'd be like to see your project come to life in real silicon? Or are you simply enthusiastic about design and wanting to learn more about System-on-Chip (SoC)s, end-to-end integration, or the Berkeley open source VLSI ecosystem? If so, keep reading!
----
Course Description

This project-based course is a follow up to EECS 151: Introduction to Digital Design and Integrated Circuits, where students learn principles, components, and methodologies for large scale digital system design. Students who designed a CPU core in the EECS151 ASIC (application specific integrated circuits) lab integrate their core into a larger System-on-Chip (SoC) using agile hardware design tools such as Chipyard and Chisel, a hardware construction language. While covering the basics of VLSI flows and parameterizable computer architecture, the course focuses on a very hands-on approach and aims to tapeout an SoC utilizing the EECS151 cores by end of semester.

Recommended Prerequisites

This rigorous course is designed for students who have completed EECS 151 LA ASIC or EE 194/290C (the original Tapeout course or Bringup). Students who instead completed EECS 151 LB FPGA are welcome but may have a higher learning curve and will be working with the cores of ASIC students. Students who have not completed EECS 151 are recommended to take this Decal another semester. Those unsure are welcome to email us. We are extremely welcoming to self-motivated students of various backgrounds but do wish to emphasize that in the first iteration of this course, background knowledge will be helpful.

Course Objectives

As this is the first iteration of the course, the first cohort focuses on a rigorous hands-on dive into the Chipyard ecosystem of parameterizable hardware generators, the Chisel hardware description language, and implementation of a Hammer VLSI flow for the open-source SKY130 process development kit. Those with tapeout experience may help develop course content, while those with EECS151 experience only will be integrating ASIC cores into Chipyard with the mentorship of more advanced students. While there may be occasional mini-lectures, the focus of this course is a hands-on project - a real SoC tapeout.

Course Structure

This course spans 13 weeks. Class meets for two hours once a week. Each class begins with
a short mini lecture, overview of project status, and check-ins with each team on milestones and obstacles. Students are expected to spend a bit more time each week outside of class time working on their project. There will be a presentation and tapeout poster at the end of the semester - and possibly a SKY130 tapeout.

An enrollment form will be made available before the first class. Enrollment will be balanced to ensure an even distribution of experience levels. If there is capacity remaining, students may request enrollment up until the add/drop deadline. Enrollment priority will be given to matriculated students over concurrent enrollment students due to department policy. Please contact us for details and concerns.